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LT1469 1 the lt ? 1469 is a dual, precision high speed operational amplifier with 16-bit accuracy and 900ns settling to 150 m v for 10v steps. this unique blend of precision and ac performance makes the LT1469 the optimum choice for high accuracy applications such as dac current-to-volt- age conversion and adc buffers. the initial accuracy and drift characteristics of the input offset voltage and invert- ing input bias current are tailored for inverting applica- tions. the 90mhz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. in noninverting appli- cations such as an adc buffer, the low distortion and dc accuracy allow full 16-bit ac and dc performance. the 22v/ m s slew rate of the LT1469 improves large signal performance compared to other precision op amps in applications such as active filters and instrumentation amplifiers. the LT1469 is manufactured on linear technologys complementary bipolar process and is available in 8-pin pdip and so packages. a single version, the lt1468, is also available. n precision instrumentation n high accuracy data acquisition systems n 16-bit dac current-to-voltage converter n adc buffer n low distortion active filters n photodiode amplifiers , ltc and lt are registered trademarks of linear technology corporation. n 90mhz gain bandwidth, f = 100khz n maximum input offset voltage: 125 m v n settling time: 900ns (a v = C1, 150 m v, 10v step) n 22v/ m s slew rate n low distortion: C96.5db for 100khz, 10v p-p n maximum input offset voltage drift: 3 m v/ c n maximum inverting input bias current: 10na n minimum dc gain: 300v/mv n minimum output swing into 2k: 12.8v n unity-gain stable n input noise voltage: 5nv/ ? hz n input noise current: 0.6pa/ ? hz n total input noise optimized for 1k w < r s < 20k w n specified at 5v and 15v supplies dual 90mhz, 22v/ m s 16-bit accurate operational amplifier applicatio s u features typical applicatio u descriptio u 16-bit dac i-to-v converter and reference inverter for bipolar output swing (v out = C10v to 10v) 15pf 2.4 s settling time to 1lsb on 20v step r lpf ltc1597 16 bits dac inputs v ref 1469 ta02 15pf c lpf v out + + 1/2 LT1469 1/2 LT1469 12k 12k 12k 12k ?5v 15v frequency (hz) 90 signal/(noise + distortion) (db) 70 50 40 10 1k 10k 100k 1469 ta02a 110 100 60 80 100 dac input code = all zeros v ref = 20v p-p 500khz filter 80khz filter 30khz filter bipolar multiplying mode signal-to-(noise + distortion)
LT1469 2 total supply voltage (v + to v C ) .............................. 36v input current (note 2) ........................................ 10ma output short-circuit duration (note 3) ............ indefinite operating temperature range (note 4) .. C 40 c to 85 c specified temperature range (note 5) ... C 40 c to 85 c maximum junction temperature .......................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number s8 part marking t jmax = 150 c, q ja = 130 c/w (n8) t jmax = 150 c, q ja = 190 c/w (s8) consult factory for military grade parts. 1469 1469i LT1469cs8 LT1469is8 LT1469cn8 LT1469in8 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics t a = 25 c, v cm = 0v unless otherwise noted. symbol parameter conditions v supply min typ max units v os input offset voltage 15v 50 125 m v 5v 50 200 m v i os input offset current 5v to 15v 13 50 na i b C inverting input bias current 5v to 15v 3 10 na i b + noninverting input bias current 5v to 15v C10 40 na input noise voltage 0.1hz to 10hz 5v to 15v 0.3 m v p-p e n input noise voltage density f = 10khz 5v to 15v 5 nv/ ? hz i n input noise current density f = 10khz 5v to 15v 0.6 pa/ ? hz r in input resistance common mode, v cm = 12.5v 15v 100 240 m w differential 15v 50 150 k w c in input capacitance 15v 4 pf v cm input voltage range (positive) guaranteed by cmrr 15v 12.5 13.5 v 5v 2.5 3.6 v input voltage range (negative) guaranteed by cmrr 15v C14.3 C12.5 v 5v C4.4 C2.5 v cmrr common mode rejection ratio v cm = 12.5v 15v 96 110 db v cm = 2.5v 5v 96 112 db minimum supply voltage guaranteed by psrr 2.5 4.5 v psrr power supply rejection ratio v s = 4.5v to 15v 100 112 db a vol large-signal voltage gain v out = 12.5v, r l = 10k 15v 300 2000 v/mv v out = 12.5v, r l = 2k 15v 300 2000 v/mv v out = 2.5v, r l = 10k 5v 200 8000 v/mv v out = 2.5v, r l = 2k 5v 200 8000 v/mv v out maximum output swing r l = 10k, 1mv overdrive 15v 13.0 13.6 v r l = 2k, 1mv overdrive 15v 12.8 13.5 v r l = 10k, 1mv overdrive 5v 3.0 3.7 v r l = 2k, 1mv overdrive 5v 2.8 3.6 v i out maximum output current v out = 12.5v, 1mv overdrive 15v 15 22 ma v out = 2.5v, 1mv overdrive 5v 15 22 ma i sc output short-circuit current v out = 0v, 0.2v overdrive (note 3) 15v 25 40 ma 1 2 3 4 8 7 6 5 top view v + out b in b +in b out a in a +in a v s8 package 8-lead plastic so n package 8-lead pdip a b
LT1469 3 symbol parameter conditions v supply min typ max units electrical characteristics t a = 25 c, v cm = 0v unless otherwise noted. symbol parameter conditions v supply min typ max units v os input offset voltage 15v l 350 m v 5v l 350 m v d v os / d t input offset voltage drift (note 8) 15v l 15 m v/ c 5v l 13 m v/ c i os input offset current 5v to 15v l 80 na d i os / d t input offset current drift (note 8) 5v to 15v l 60 pa/ c i b C inverting input bias current 5v to 15v l 20 na d i b C/ d t inverting input bias current drift (note 8) 5v to 15v l 40 pa/ c i b + noninverting input bias current 5v to 15v l 60 na v cm input voltage range (positive) guaranteed by cmrr 15v l 12.5 v 5v l 2.5 v input voltage range (negative) guaranteed by cmrr 15v l C12.5 v 5v l C2.5 v sr slew rate a v = C10, r l = 2k (note 6) 15v 15 22 v/ m s 5v 11 17 v/ m s fpbw full-power bandwidth 10v peak, (note 7) 15v 350 khz 3v peak, (note 7) 5v 900 khz gbw gain bandwidth product f = 100khz, r l = 2k 15v 60 90 mhz 5v 55 88 mhz t r , t f rise time, fall time a v = 1, 10% to 90%, 0.1v step 15v 11 ns 5v 12 ns os overshoot a v = 1, 0.1v step 15v 30 % 5v 35 % t pd propagation delay a v = 1, 50% v in to 50% v out , 0.1v step 15v 9 ns 5v 10 ns t s settling time 10v step, 0.01%, a v = C1 15v 760 ns 10v step, 150 m v, a v = C1 15v 900 ns 5v step, 0.01%, a v = C1 5v 770 ns thd total harmonic distortion a v = C1, v out = 10v p-p , f = 100khz 15v C 96.5 db a v = 1, v out = 20v p-p , f = 1khz 15v C 125 db r out output resistance a v = 1, f = 100khz 15v 0.02 w channel separation v out = 12.5v, r l = 2k 15v 100 130 db v out = 2.5v, r l = 2k 5v 100 130 db i s supply current per amplifier 15v 4.1 5.2 ma 5v 3.8 5 ma d v os input offset voltage match 15v 30 225 m v 5v 50 350 m v d i b C inverting input bias current match 5v to 15v 2 18 na d i b + noninverting input bias current match 5v to 15v 5 78 na d cmrr common mode rejection match v cm = 12.5v (note 9) 15v 93 113 db v cm = 2.5v (note 9) 5v 93 115 db d psrr power supply rejection match v s = 4.5v to 15v (note 9) 97 115 db the l denotes the specifications which apply over the temperature range 0 c t a 70 c, v cm = 0v unless otherwise noted.
LT1469 4 symbol parameter conditions v supply min typ max units the l denotes the specifications which apply over the temperature range 0 c t a 70 c, v cm = 0v unless otherwise noted. electrical characteristics cmrr common mode rejection ratio v cm = 12.5v 15v l 94 db v cm = 2.5v 5v l 94 db minimum supply voltage guaranteed by psrr l 4.5 v psrr power supply rejection ratio v s = 4.5v to 15v l 95 db a vol large-signal voltage gain v out = 12.5v, r l = 10k 15v l 100 v/mv v out = 12.5v, r l = 2k 15v l 100 v/mv v out = 2.5v, r l = 10k 5v l 100 v/mv v out = 2.5v, r l = 2k 5v l 100 v/mv v out maximum output swing r l = 10k, 1mv overdrive 15v l 12.9 v r l = 2k, 1mv overdrive 15v l 12.7 v r l = 10k, 1mv overdrive 5v l 2.9 v r l = 2k, 1mv overdrive 5v l 2.7 v i out maximum output current v out = 12.5v, 1mv overdrive 15v l 12.5 ma v out = 2.5v, 1mv overdrive 5v l 12.5 ma i sc output short-circuit current v out = 0v, 0.2v overdrive (note 3) 15v l 17 ma sr slew rate a v = C10, r l = 2k (note 6) 15v l 13 v/ m s 5v l 9v/ m s gbw gain bandwidth product f = 100khz, r l = 2k 15v l 55 mhz 5v l 50 mhz channel separation v out = 12.5v, r l = 2k 15v l 98 db v out = 2.5v, r l = 2k 5v l 98 db i s supply current per amplifier 15v l 6.5 ma 5v l 6.3 ma d v os input offset voltage match 15v l 600 m v 5v l 600 m v d i b C inverting input bias current match 5v to 15v l 38 na d i b + noninverting input bias current match 5v to 15v l 118 na d cmrr common mode rejection match v cm = 12.5v (note 9) 15v l 91 db v cm = 2.5v (note 9) 5v l 91 db d psrr power supply rejection match v s = 4.5v to 15v (note 9) l 92 db symbol parameter conditions v supply min typ max units v os input offset voltage 15v l 500 m v 5v l 500 m v d v os / d t input offset voltage drift (note 8) 15v l 16 m v/ c 5v l 15 m v/ c i os input offset current 5v to 15v l 120 na d i os / d t input offset current drift (note 8) 5v to 15v l 120 pa/ c i b C inverting input bias current 5v to 15v l 40 na d i b C/ d t inverting input bias current drift (note 8) 5v to 15v l 80 pa/ c i b + noninverting input bias current 5v to 15v l 80 na the l denotes the specifications which apply over the temperature range C 40 c t a 85 c, v cm = 0v unless otherwise noted. (note 5)
LT1469 5 the l denotes the specifications which apply over the temperature range C40 c t a 85 c, v cm = 0v unless otherwise noted. (note 5) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the inputs are protected by back-to-back diodes and two 100 w series resistors. if the differential input voltage exceeds 0.7v, the input current should be limited to less than 10ma. input voltages outside the supplies will be clamped by esd protection devices and input currents should also be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. note 4: the LT1469c and LT1469i are guaranteed functional over the operating temperature range of C 40 c to 85 c. note 5: the LT1469c is guaranteed to meet specified performance from 0 c to 70 c and is designed, characterized and expected to meet specified performance from C 40 c to 85 c but is not tested or qa sampled at these temperatures. the LT1469i is guaranteed to meet specified performance from C 40 c to 85 c. note 6: slew rate is measured between 8v on the output with 12v swing for 15v supplies and 2v on the output with 3v swing for 5v supplies. note 7: full-power bandwidth is calculated from the slew rate. fpbw = sr/2 p v p . note 8: this parameter is not 100% tested. note 9: d cmrr and d psrr are defined as follows: 1) cmrr and psrr are measured in m v/v on each amplifier; 2) the difference between the two sides is calculated in m v/v; 3) the result is converted to db. electrical characteristics v cm input voltage range (positive) guaranteed by cmrr 15v l 12.5 v 5v l 2.5 v input voltage range (negative) guaranteed by cmrr 15v l C12.5 v 5v l C2.5 v cmrr common mode rejection ratio v cm = 12.5v 15v l 92 db v cm = 2.5v 5v l 92 db minimum supply voltage guaranteed by psrr l 4.5 v psrr power supply rejection ratio v s = 4.5v to 15v l 93 db a vol large-signal voltage gain v out = 12,5v, r l = 10k 15v l 75 v/mv v out = 12.5v, r l = 2k 15v l 75 v/mv v out = 2.5v, r l = 10k 5v l 75 v/mv v out = 2.5v, r l = 2k 5v l 75 v/mv v out maximum output swing r l = 10k, 1mv overdrive 15v l 12.8 v r l = 2k, 1mv overdrive 15v l 12.6 v r l = 10k, 1mv overdrive 5v l 2.8 v r l = 2k, 1mv overdrive 5v l 2.6 v i out maximum output current v out = 12.5v, 1mv overdrive 15v l 7ma v out = 2.5v, 1mv overdrive 5v l 7ma i sc output short-circuit current v out = 0v, 0.2v overdrive (note 3) 15v l 12 ma sr slew rate a v = C10, r l = 2k (note 6) 15v l 9v/ m s 5v l 6v/ m s gbw gain bandwidth product f = 100khz, r l = 2k 15v l 45 mhz 5v l 40 mhz channel separation v out = 12.5v, r l = 2k 15v l 96 db v out = 2.5v, r l = 2k 5v l 96 db i s supply current per amplifier 15v l 7ma 5v l 6.8 ma d v os input offset voltage match 15v l 800 m v 5v l 800 m v d i b C inverting input bias current match 5v to 15v l 78 na d i b + noninverting input bias current match 5v to 15v l 158 na d cmrr common mode rejection match v cm = 12.5v (note 9) 15v l 89 db v cm = 2.5v (note 9) 5v l 89 db d psrr power supply rejection match v s = 4.5v to 15v (note 9) l 90 db symbol parameter conditions v supply min typ max units
LT1469 6 typical perfor a ce characteristics uw 0.1hz to 10hz voltage noise time (1s/div) voltage noise (100nv/div) 1469 g06 v s = 15v t a = 25 c input noise spectral density frequency (hz) 1 1 input voltage noise (nv/ ? hz) input current noise (pa/ ? hz) 100 1000 10 100 1k 10k 100k 1469 g05 10 0.01 1 i n e n 10 0.1 v s = 15v t a = 25 c a v = 101 r s = 100k for i n source resistance, r s ( w ) 1 total noise voltage (nv/ ? hz) 10 10 1k 10k 100k 1469 g36 0.1 100 100 v s = 15v t a = 25 c f = 10khz total noise resistor noise only r s + total noise vs unmatched source resistance input common mode voltage (v) ?5 input bias current (na) ?0 0 20 0 10 1469 g03 ?0 ?0 ?0 ?0 5 5 40 i b i b + 60 80 15 v s = 15v t a = 25 c input bias current vs input common mode voltage temperature ( c) ?0 0 10 i b i b + 30 25 75 1469 g04 ?0 ?0 ?5 0 50 100 125 ?0 ?0 20 input bias current (na) v s = 15v input bias current vs temperature supply voltage ( v) 0 supply current (ma) 1469 g01 5 10 15 20 6 5 4 3 2 1 85 c 25 c ?0 c supply current vs supply voltage and temperature supply voltage ( v) 0 v common mode range (v) 1.0 2.0 2.0 3 6 912 1469 g02 15 1.0 0.5 1.5 1.5 v + 0.5 18 t a = 25 c d v os < 100 m v input common mode range vs supply voltage input offset voltage ( v) 175 percentage of units (%) 125 ?5 ?5 25 75 125 175 50 40 30 20 10 0 1469 g37 v s = 15v t a = 25 c inverting input bias current (na) ?0 percentage of units (%) 7.5 ? 2.5 0 2.5 5 7.5 10 40 30 20 10 0 1469 g38 v s = 15v t a = 25 c distribution of inverting input bias current distribution of input offset voltage
LT1469 7 typical perfor a ce characteristics uw output short-circuit current vs temperature settling time to 0.01% vs output step, v s = 15v output voltage swing vs supply voltage output voltage swing vs load current supply voltage ( v) 0 1 v output voltage swing (v) 4 3 2 ? ? ? v + ? 5 1469 g10 10 15 20 r l = 2k r l = 10k r l = 10k t a = 25 c r l = 2k output current (ma) ?0 v ? 0.5 output voltage swing (v) 1.0 2.0 2.5 v + 0.5 2.0 ?0 0 5 1469 g11 1.5 ?.5 1.0 2.5 ?5 5 10 15 20 v s = 15v 85 c 85 c 25 c 25 c ?0 c ?0 c temperature ( c) ?0 10 output short-circuit current (ma) 15 25 30 35 60 45 0 50 75 1469 g12 20 50 55 40 ?5 25 100 125 v s = 15v v in = 0.2v source sink settling time (ns) 0 output step (v) 2 6 10 800 1469 g13 ? ? 0 4 8 ? ? ?0 200 400 600 1000 a v = 1 a v = 1 a v = 1 a v = 1 v s = 15v t a = 25 c r l = 1k settling time to 0.01% vs output step, v s = 5v settling time (ns) 300 output step (v) 1 3 5 700 1469 g14 ? ? 0 2 4 ? ? ? 400 500 600 800 a v = 1 a v = 1 a v = 1 a v = 1 v s = 5v t a = 25 c r l = 1k settling time to 150 m v vs output step settling time (ns) 0 output step (v) 2 6 10 800 1469 g15 ? ? 0 4 8 ? ? ?0 200 400 600 1000 v s = 15v t a = 25 c a v = 1 r f = r g = 2k c f = 8pf load resistance ( w ) 10 110 open-loop gain (db) 130 135 140 100 1k 10k 1469 g08 125 120 115 t a = 25 c v s = 5v v s = 15v open-loop gain vs resistive load open-loop gain vs temperature temperature ( c) ?0 130 140 160 25 75 1469 g09 120 110 ?5 0 50 100 125 100 90 150 open-loop gain (db) r l = 2k v s = 5v v s = 15v frequency (hz) 10 gain (db) 100 1k 10k 100k 1m 10m 100m 140 120 100 80 60 40 20 0 ?0 1469 g39 t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf r l = 2k v s = 5v v s = 15v open-loop gain vs frequency
LT1469 8 typical perfor a ce characteristics uw open-loop gain and phase vs frequency frequency (hz) 20 gain (db) phase (deg) 40 50 70 10k 1m 10m 100m 1469 g16 0 100k 60 30 10 ?0 0 40 60 100 ?0 80 20 ?0 ?0 phase gain 15v 15v 5v 5v t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf r l = 2k supply voltage ( v) 0 gain bandwidth (mhz) phase margin (deg) 90 92 20 1469 g17 88 86 82 5 10 15 84 36 38 40 34 32 t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf r l = 2k phase margin gain bandwidth gain bandwidth and phase margin vs supply voltage temperature ( c) ?5 84 gain bandwidth (mhz) phase margin (deg) 86 90 92 94 0 50 75 1469 g18 88 32 34 36 40 30 42 38 ?5 25 100 125 v s = 5v v s = 5v v s = 15v v s = 15v gain bandwidth phase margin gain bandwidth and phase margin vs temperature gain vs frequency, a v = 1 gain vs frequency, a v = 1 frequency (hz) 100k 2 gain (db) 4 6 8 10 1m 10m 100m 1469 g24 0 ? ? ? 12 14 v s = 15v t a = 25 c a v = 1 no r l 100pf 10pf 50pf 20pf gain vs frequency, a v = C1 frequency (hz) 100k 2 gain (db) 4 6 8 10 1m 10m 100m 1469 g25 0 ? ? ? 12 14 v s = 15v t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf no r l 300pf 200pf 50pf 100pf frequency (hz) 100k ? gain (db) 0 1 2 3 1m 10m 100m 1469 g22 ? ? ? ? 4 5 t a = 25 c a v = 1 r l = 2k v s = 5v v s = 15v gain vs frequency, a v = C 1 frequency (hz) 100k ? gain (db) 0 1 2 3 1m 10m 100m 1469 g23 ? ? ? ? 4 5 t a = 25 c a v = 1 r l = 2k c f = 5pf r f = r g = 2k v s = 5v v s = 15v r f = r g = 5.1k v s = 5v v s = 15v slew rate vs supply voltage supply voltage ( v) 0 slew rate (v/ m s) 22 24 26 20 1469 g26 20 18 14 5 10 15 16 30 28 ?r +sr t a = 25 c a v = 1 r l = 2k slew rate vs temperature temperature ( c) ?0 slew rate (v/ m s) 40 25 1469 g27 25 ?r +sr 15 ?5 0 50 10 5 45 35 30 20 75 100 125 v s = 15v a v = 1 r l = 2k
LT1469 9 typical perfor a ce characteristics uw common mode rejection ratio vs frequency frequency (hz) 100 0 common mode rejection ratio (db) 20 40 60 80 120 1k 10k 100k 1m 1469 g21 10m 100m 100 v s = 15v t a = 25 c r l = 2k frequency (hz) 100 power supply rejection ratio (db) 60 80 100 100k 10m 1469 g20 40 20 0 1k 10k 1m 120 140 160 100m psrr +psrr v s = 15v t a = 25 c r l = 2k undistorted output swing vs frequency, v s = 5v frequency (khz) 1 4 output voltage swing (v p-p ) 5 6 7 8 10 100 1000 1469 g33 3 2 1 0 9 10 v s = 5v t a = 25 c r l = 2k thd < 1% a v = 1 a v = 1 undistorted output swing vs frequency, v s = 15v frequency (khz) 1 0 output voltage swing (v p-p ) 20 25 30 10 100 1000 1469 g30 15 10 5 a v = 1 a v = 1 v s = 15v t a = 25 c r l = 2k thd < 1% output impedance vs frequency frequency (hz) 0.01 output impedance ( w ) 0.1 1 10 100 10k 1m 10m 100m 1469 g19 0.001 100k v s = 15v t a = 25 c a v = 100 a v = 10 a v = 1 frequency (hz) 100 total harmonic distortion (db) 1k 10k 100k 1469 g28 ?0 ?0 100 110 120 130 v s = 15v a v = 2 r l = 2k v out = 10v p-p total harmonic distortion vs frequency total harmonic distortion + noise vs amplitude output signal (v rms ) 0.01 110 thd + noise (db) ?0 ?0 ?0 0.1 1 10 1469 g29 ?0 ?0 100 v s = 15v v s = 5v t a = 25 c a v = 1 r l = 600 w f = 10khz noise bw = 80khz warm-up drift vs time time after power up (s) 0 20 40 60 80 100 120 140 offset voltage drift ( m v) 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 1469 g07 s0-8 15v n8 5v s0-8 5v n8 15v frequency (hz) 100 channel separation (db) 1k 10k 100k 1m 10m 100m 140 120 100 80 60 40 20 0 1469 g39 v s = 15v t a = 25 c r l = 2k channel separation vs frequency power supply rejection ratio vs frequency
LT1469 10 applicatio s i for atio wu u u layout and passive components the LT1469 requires attention to detail in board layout in order to maximize dc and ac performance. for best ac results (for example, fast settling time) use a ground plane, short lead lengths and rf quality bypass capacitors (0.01 m f to 0.1 m f) in parallel with low esr bypass capaci- tors (1 m f to 10 m f tantalum). for best dc performance, use star grounding techniques, equalize input trace lengths and minimize leakage (e.g., 1.5g w of leakage between an input and a 15v supply will generate 10naequal to the maximum i b C specification). board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: for inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below). microvolt level error voltages can also be generated in the external circuitry. thermocouple effects caused by tem- perature gradients across dissimilar metals at the con- tacts to the inputs can exceed the inherent drift of the amplifier. air currents over device leads should be mini- mized, package leads should be short and the two input leads should be as close together as possible and main- tained at the same temperature. typical perfor a ce characteristics uw small-signal transient, a v = 1 v s = 15v 1469 g31 small-signal transient, a v = C 1 v s = 15v 1469 g32 large-signal transient, a v = 1 v s = 15v 1469 g34 large-signal transient, a v = C 1 v s = 15v 1469 g35
LT1469 11 the parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause peaking or even oscillations. for feedback resistors greater than 2k, a feedback capacitor of value c f > r g ? c in /r f should be used to cancel the input pole and optimize dynamic performance. for applications where the dc noise gain is one, and a large feedback resistor is used, c f should be greater than or equal to c in . an example would be a dac i-to-v converter as shown on the front page of the data sheet where the dac can have many tens of picofarads of output capacitance. another example would be a gain of C1 with 5k resistors; a 5pf to 10pf capacitor should be added across the feedback resistor. input considerations each input of the LT1469 is protected with a 100 w series resistor and back-to-back diodes across the bases of the input devices. if large differential input voltages are antici- pated, limit the input current to less than 10ma with an external series resistor. each input also has two esd clamp diodesone to each supply. if an input is driven beyond the supply, limit the current with an external resistor to less than 10ma. applicatio s i for atio wu u u q1 +in 1469 f02 r1 100 q2 ?n r1 100 v v + figure 2. input stage protection the LT1469 employs bias current cancellation at the inputs. the inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as i-to-v converters. the noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. as the input offset current can be greater than either input current, the use of balanced source resistance is not recommended as it actually degrades dc accuracy and also increases noise. the input bias currents vary with common mode voltage. the cancellation circuitry was not designed to track this common mode voltage because the settling time would have been adversely affected. the LT1469 inputs can be driven to the negative supply and to within 0.5v of the positive supply without phase reversal. as the input moves closer than 0.5v to the positive supply, the output reverses phase. total input noise the total input noise of the LT1469 is optimized for a source resistance between 1k and 20k. within this range, the total input noise is dominated by the noise of the source resistance itself. when the source resistance is below 1k, voltage noise of the amplifier dominates. when the source resistance is above 20k, the input noise current is the dominant contributor. + v out r f c f c in 1/2 LT1469 v in 1469 f01 r g figure 1. nulling input capacitance
LT1469 12 capacitive loading the LT1469 drives capacitive loads of up to 100pf in unity- gain and 300pf in a gain of C1. when there is a need to drive a larger capacitive load, a small series resistor should be inserted between the output and the load. in addition, a capacitor should be added between the output and the inverting input as shown in figure 3. settling time the LT1469 is a single stage amplifier with an optimal thermal layout that leads to outstanding settling perfor- mance. measuring settling even at the 12-bit level is very challenging, and at the 16-bit level requires a great deal of subtlety and expertise. fortunately, there are two excellent linear technology reference sources for settling mea- surementsapplication notes 47 and 74. appendix b of an47 is a vital primer on 12-bit settling measurements and an74 extends the state-of-the-art while concentrating on settling time with a 16-bit current output dac input. the settling of the dac i-to-v converter on the front page was measured using the exact methods of an74. the optimum nulling of the dac output capacitance requires 15pf across the 12k feedback resistor. the theoretical limit for 16-bit settling is 11.1 times this rc time constant or 2 m s. the actual settling time is 2.4 m s at the output of the LT1469. the rc output noise filter adds a slight settling time delay but reduces the noise bandwidth to 1.6mhz which in- creases the output resolution for 16-bit accuracy. + v out r f r o 3 (1 + r f /r g )/(2 ?c l ?5mhz) r f 3 10r o c f = (2r o /r f )c l c f 1/2 LT1469 v in 1469 f03 c l r g r o figure 3. driving capacitive loads applicatio s i for atio wu u u
LT1469 13 + 1/2 lt1364 10k 2.1k 22pf 33.2 + 1/2 LT1469 10k 1k 22pf + 1/2 LT1469 20k 22.1k 22pf 820pf 50 feet shielded twisted pair cable parallel composite topology: lt1364 provides output current; LT1469 preserves linearity thd + n measured here 820pf + 1/2 lt1364 20k 24.3k 22pf input z in = 10k v s = 15v gain = 6db 1469 ta03 33.2 30.1 30.1 600 total harmonic distortion + noise v out frequency measurement bandwidth 0.00025% 10v rms 1khz 22khz 0.0008% 10v rms 20hz to 20khz 80khz 0.0006% 26dbu 1khz 22khz *1dbu = 1 milliwatt into 600 ultralow distortion balanced audio line driver typical applicatio s u
LT1469 14 sche atic w w si plified q10 i5 i2 i1 i4 i6 1469 ss i3 out q11 q8 q9 q7 q6 q1 in +in v + v q5 q2 q4 c bias q3 typical applicatio s u + 1/2 LT1469 15v 15v 330pf 10k 19.994k** r select *** typical 6 w 27 w output 1469 ta04 27 w 330 w 510 w 125v 1 m f 15pf 1m 50k 1m 50k 330 w 510 w 125v 1n4148 1n4148 1k q5 2n2222 q6 2n2907 q3 2n3440* q1 2n5415 q3 2n5415* 1k 50k** 50k** 50k** 50k** q2 2n3440 1 m f r fb ltc1597 16 bits v ref + 1/2 LT1469 100pf * ** *** heat sink vishay s102 resistor 0.01% 1% metal film resistor note: for further explanation, refer to application note 74, appendix h v out = 200v p-p i out = 25ma thd + n = 90db at 100hz extending 16-bit dac performance to 200v output swing
LT1469 15 n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 1098 0.100 (2.54) bsc 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) package descriptio u dimensions in inches (millimeters) unless otherwise noted. 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1469 16 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2000 1469f lt/tp 0800 4k ? printed in usa related parts typical applicatio u part number description comments lt1167 precision instrumentation amplifier single resistor gain set, 0.04% max gain error, 10ppm max gain nonlinearity lt1468 single 90mhz, 22v/ m s, 16-bit accurate op amp 75 m v max v os , single version of LT1469 ltc1595/ltc1596 16-bit serial multiplying i out dac 1lsb max inl/dnl, low glitch, dac8043 16-bit upgrade ltc1597 16-bit parallel multiplying i out dac 1lsb max inl/dnl, low glitch, on-chip bipolar resistors ltc1604 16-bit, 333ksps sampling adc 2.5v input, sinad = 90db, thd = C100db ltc1605 single 5v, 16-bit, 100ksps sampling adc low power, 10v inputs, parallel/byte interface 16-bit accurate single ended to differential adc buffer + + 2k v in 2k ?v ?v 5v 5v r s 10pf 100 100 3000pf 3000pf +in ltc1604 1/2 LT1469 1/2 LT1469 16 bits 333ksps adc outputs 1469 ta01 ?n frequency (khz) 0 1469 ta01a 20 40 60 80 100 120 140 160 amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 f sample = 333ksps v in = 1.25v f in = 100khz v s = 5v 4096 point fft of adc output

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